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CAD Engineer

Malibu, CA, USA Req #42
Monday, March 16, 2020

Located in Malibu, California, HRL has been on the leading edge of technology, conducting pioneering research and advancing the state of the art.


  • Lead integration, verification, design trade-offs, and carry out layout on critical performance elements. Implementation of GDSII custom IC layout for mixed signal ASICs comprised of digital netlists, large analog circuit macros, and custom foundry components. The digital netlist to GDSII implementations will follow traditional CAD based back-end flow such as floor-planning, P&R, synthesis, formal verification, clock tree insertion, and timing closure.

  • Ability to perform top level ASIC assembly with mixed signal components, performing power analysis, load and decoupling analysis for analog references, mixed signal clocking nets, as well as ensuring successful ground plane crossings. Interface with front end designers to assist them with customizing cad flows, Physical Design Verification methodology, and debugging LVS/DRC issues at all levels of hierarchy.

  • This role requires a fundamental understanding of circuits and mixed signal design as well as proficiency in scripting, back end digital flows, CAD tools, and foundry PDK formats.

  • In-depth knowledge in CAD/EDA tools to support team of engineers on their daily CAD issues.

  • Install and maintain and troubleshoot PDK environments for semiconductor foundries.

  • In addition to executing the above tasks the role is primarily for someone who can build and customize robust back-end flows, capturing the needs of both digital and analog circuit implementation and verification.


  • At least 6 years as lead engineer with demonstrable experience in:

  • CMOS and bipolar transistor design, analog circuit theory, deep sub-micron logic, and memory fault models.

  • Strong background in performing full custom analog IC layout.

  • Verification techniques for mixed signal VLSI ASIC designs.

  • Proficient in perl/tcl/python or other scripting language and in Verilog/VHDL and C/C++

  • Track record in performing digital back end flows: Floorplanning, placement, synthesis, timing closure, and power/area optimization

  • Expert in block and top level floor planning, global power/clock routing, and pad frame construction

  • Expert in CAD tools, simulation and debug tools, design databases, file formats, back end flows

  • Support semiconductor design engineers in CAD/EDA issue and maintain tools, licenses, storage and compute servers

  • Install and manage EDA license servers and simulation tools (Cadence, Synopsys, Calibre and other EDA/CAD related tools)

  • Expert in debug and verify LVS, DRC, ERC, Density/Antenna/Stitching, taking a AISC design completely through physical design to tapeout

  • Full custom circuit, block, and chip layout using Cadence Virtuoso tools, Layout L/XL, and physical verification tools Assura and Calibre

  • Capable of customizing/generating standard cells for automated digital design flows

  • Experience with custom device generation (eg. transistors, diodes, resistors, capacitors, MEM structures)


  • Familiarity with semiconductor IC technologies (e.g., SiGe BiCMOS, CMOS).

  • Understanding of circuit design techniques, semiconductor device physics, signal processing,

  • Experience with Linux workstation environment

  • Use diverse laboratory tools for IC evaluation and debugging


  • Proficiency in use of computers, engineering work stations, complex electronic equipment, oral and written communication, interaction with vendors/colleagues and willingness to work in a fast-paced, deadline-driven environment.

  • Ability to work well in a team and independently.

EDUCATION DESIRED: BS or MS., Electrical Engineering


U.S. citizenship is required. Must be able to obtain and maintain a security clearance. Active SSBI is a plus.            

Keywords: "physical design engineer", "cad support", AMS, ASIC, mixed-signal, analog, place, route,


This position must meet Export Control compliance requirements, therefore a "U.S. Person" as defined by 22 C.F.R. § 120.15 is required. "U.S. Person" includes U.S. Citizen, lawful permanent resident, refugee, or asylee.
We are proud to be an EEO/AA employer M/F/D/V. We maintain a drug-free workplace and perform pre-employment substance abuse testing.

Other details

  • Pay Type Salary
  • Malibu, CA, USA